1. Field of the Invention
The present invention pertains to the field of power management in a semiconductor environment. More particularly, the invention pertains to a system and method for adaptive scaling of voltages, clock speeds, and other electrical factors within an integrated circuit in order to dynamically minimize power consumption while maintaining optimum performance.
2. Background Art
For virtually all electronics applications, it is desirable to minimize power consumption. In terms of system design and performance, reduced power consumption results in less heat being generated. This increases system life, reduces requirements for cooling systems. A reduction in power supply requirements also enables smaller, more compact design. Further, any reduction in the power consumed by a circuit component, such as an integrated circuit (IC) or a module within an IC, will improve the performance and reliability of prior circuit stages which feed into the IC or IC module. Further, for portable devices such as laptop computers, media players, and cell phones, reduced power consumption contributes to longer battery life and also enables additional functionality for a given power supply. From a societal standpoint, even incremental reductions in power consumption contribute to conservation of energy resources.
There are a number of conventional strategies for reducing power consumption within integrated circuits. One strategy is to identify a module(s) within an IC which has not drawn power for some determined period of time, or which is not anticipated to draw power for some future period of time (or both), and to either reduce or shut off the power supply to the module. If the module is fed by a single power supply, then this strategy may only be viable if no components or submodules within the module are expected to require power during this period of time. If any submodule or component within the module is expected to require power, it may be necessary to maintain a supply of power to the entire module. (In some cases, the “module” may constitute the entire IC as a whole.)
Another conventional power reduction strategy is to reduce the power supplied to the IC or to a module within the IC. In virtually all cases, this will result in some kind of reduction in system performance, for example lower clock speeds for digital chips or reduced range for a radio frequency (RF) chip. Depending on the application for which the IC is being used, or depending on the particular function of a module within an IC, in some cases the reduction in system performance will have no noticeable impact from a user perspective. For example, a user using a portable computer for word processing may not notice a reduction in the clock speed of the system microprocessor. Clearly, however, for some applications—such as popular video applications or voice-to-text translation, to name just two of many examples—it is desirable to maintain maximum performance from an IC, for example, to maintain maximum clock speed from a microprocessor or a Digital Signal Processor (DSP) chip. For these applications, any attempts at power savings through reduced supply voltages may have a notable impact, and sometimes an unacceptable impact, on system performance in relation to the requirements of the user application.
What is needed, then, is a system and method for providing on-chip power management for an integrated circuit, where the system and method minimize any negative impact on system performance, and where the system and method take better advantage of the variable levels of voltages or clock speeds which may be required by transistors and other elements within the IC package.